1. Field of the Invention
The present invention relates to a complementary insulated gate field effect semiconductor device and a method of manufacturing the same. More specifically the present invention relates to an improved complementary insulated gate field effect semiconductor device and a method for manufacturing the same employing ion implantation.
2. Description of the Prior Art
A process for manufacturing an example of a conventional complementary insulated gate field effect semiconductor device is shown in FIGS. 1a to 1e which illustrate sectional views of the semiconductor device at various stages of the manufacturing process.
Referring first to FIG. 1(a), a semiconductor substrate 1 of an N conductivity type is formed, partially in the vicinity of the surface, of a well 2 of a P conductivity type by means of a well known ion implantation process. Referring to FIG. 1(b), then a source and drain regions 3 and 4 of a P.sup.+ conductivity type are formed at the original substrate area in the vicinity of the surface by means of a well known selective diffusion process, thereby to provide a first insulated gate field effect transistor comprising the source and drain regions 3 and 4. Again referring to FIG. 1(b), a guard region 5 of a P.sup.+ conductivity type surrounding the well region 2 and another guard region 6 of a P.sup.+ conductivity type surrounding a second insulated gate field effect transistor to be formed within the well 2 to be described below are also formed at the same time.
Referring to FIG. 1(c), a source and drain regions 7 and 8 of an N.sup.+ conductivity type are formed in the well 2 in the vicinity of the surface to form the second insulated gate field effect transistor. Referring to FIG. 1(c), a further guard region 9 of an N.sup.+ conductivity type is also formed at the same time surrounding the first insulated gate field effect transistor. Referring to FIG. 1(d), a thick oxide film 10 is then formed on the surface of the original semiconductor substrate 1 and on the well region 2, while thin gate oxide films 11 and 12 are formed on the channel regions of the first and second insulated gate field effect transistors. Referring finally to FIG. 1(e), source and drain electrodes 13, 14, 15 and 16 are provided in ohmic contact with the source and drain regions of the first and second insulated gate field effect transistors and gate electrodes 17 and 18 are also provided on the gate oxide films 11 and 12.
According to the above described conventional method for manufacturing a complementary insulated gate field effect semiconductor device, the threshold voltages of the respective insulated gate field effect transistors are determined as a function of the impurity concentrations in the original semiconductor substrate 1 and the well region 2, the thickness of the gate oxide film and the surface state density. Therefore, it is extremely difficult to make certain that threshold voltages of both insulated gate field effect transistors are the same.
The conventional complementary insulated gate field effect semiconductor device as described above also employs guard regions 6 and 9 surrounding the respective insulated gate field effect transistors for the purpose of preventing a parasitic MOS action occurring in the same region between the insulated gate field effect transistors. However, employment of such guard regions 6 and 9 degrades the degree of integration of an integrated circuit. Nevertheless, omission of these guard regions 6 and 9 could cause a parasitic MOS action. With a view to increasing the degree of integration of any integrated circuit, one could think of overlapping, in part, the guard regions 5, 6 and 9 and the source or drain regions in both of the above described insulated gate field effect transistors. However, partial overlapping of these guard regions 5, 6 and 9 causes the formation of a high concentration junction, which decreases the breakdown voltage between the respective insulated gate field effect transistors to about 6 volts. On the other hand, an attempt to separate the above described guard regions 5 and 9 with a view to increasing the breakdown voltage decreases the degree of integration of an integrated circuit.